(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the improvement of sidewalls roughness of a polysilicon gate electrode.
(2) Description of the Prior Art
Conventional methods of creating a gate electrode are well known in the art. The process conventionally starts with the creation of a layer of gate dielectric or pad oxide over the surface of a substrate, a layer of gate material typically comprising polysilicon is deposited over the layer of pad oxide. To provide the deposited layer of polysilicon with a desired level of conductivity, the layer of polysilicon can be in-situ doped with impurity. To further reduce the resistance of the layer of doped polysilicon, the surface of the patterned and etched layer of polysilicon is salicided creating for instance a layer of tungsten silicide over the surface of the layer of polysilicon. The deposited layer of polysilicon is patterned and etched using methods of photolithographic patterning after which Reactive Ion Etching (RIE) removes excess polysilicon in accordance with a photoresist mask. The etching of the layer of polysilicon creates a layer of polysilicon having sidewalls, these sidewalls have a degree of roughness that is determined by the grain structure of the polysilicon at the time that the RIE is applied. For increasingly reduced device dimensions, the grain size of the etched layer of polysilicon that is exposed in the sidewalls of the etched polysilicon has a negative impact on device performance since the grain size approaches the device line width. The relatively poor control that is achieved in this manner of the Critical Dimension of the polysilicon gate has a negative effect on critical gate performance parameters such as the gate threshold voltage (Vt) and the drain saturation current (Idsat). One of the solutions that have been applied to solve this concern is the use of amorphous silicon as part of the structure of the layer of gate material. This solution however, although it results in improved smoothness of the sidewalls of the created gate structure, leads to polysilicon depletion resulting in increased gate polysilicon capacitance and increased threshold voltage.
Methods have been provided for the creation of gate electrodes such as first etching a layer of polysilicon and then applying an anisbtropic etch to remove the undesirable rough outer surface of the sidewalls of the gate electrode. This anisotropic etch however results in a tapered gate profile which is not desirable. Another approach is to initially reduce the grain size of the applied layer of polysilicon by using a pre-amorphizing impurity implantation. The above referred to method of using both polysilicon and amorphized silicon for the creation of a gate electrode has also been explored in the art.
All of these methods however are typically cumbersome and expensive to implement or have unacceptable side effects such as creating undesirable gate profiles. A simple method is therefore required that removes the effect of surface granularity in the sidewalls of patterned and etched layers of polysilicon. The invention provides such a method by providing a step of oxidation as part of the process of creating a gate electrode of polysilicon.
U.S. Pat. No. 6,221,746 B1 (Huang et al.) shows a poly gate process with an anneal to produce smooth poly sidewalls.
U.S. Pat. No. 5,612,249 (Sun et al.) reveals a gate process with an oxide spacer on the poly gate sidewall.
U.S. Pat. No. 5,902,125 (Wu) and U.S. Pat. No. 5,897,975 (Karlsson et al.) are related gate patents.
U.S. Pat. No. 5,548,132 (Batra et al.) shows a smooth poly gate with small grains.
U.S. Pat. No. 6,200,887 B1 (Balasubramaniam et al.) shows a method to form a smooth poly gate sidewalls.
A principle objective of the invention is to create a polysilicon gate electrode having smooth sidewalls by amorphizing the sidewalls of the gate electrode structure.
Another objective of the invention is to create a polysilicon gate electrode having smooth sidewalls whereby the gate material is not subject to effects of gate depletion.
Yet another objective of the invention is to create a polysilicon gate electrode having smooth sidewalls for gate electrodes having sub-micron and deep sub-micron device feature size.
A still further objective of the invention is to improve Critical Dimension control of a polysilicon gate electrode having sub-micron and deep sub-micron device feature size.
In accordance with the objectives of the invention a new step is provided for the creation of polysilicon gate electrode structures. A layer of polysilicon is deposited over the surface of a layer of semiconductor material, the layer of polysilicon is etched using a layer of hardmask material for this purpose. The etch of the layer of polysilicon is performed using a dual power source plasma system. During the etching of the layer of polysilicon, a step of inert oxidation is inserted, this step forms a layer of passivation over the sidewalls of the etched layer of polysilicon. The step of inert oxidation is an oxygen-based plasma exposure.